The present application relates to a semiconductor device and a method of forming the same. More particularly, the present application relates to a semiconductor device including a stacked nanowire n-type field effect transistor and a stacked nanowire p-type field effect transistor located on different portions of a semiconductor substrate and a method of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, gate-all-around semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor nanowire field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In its basic form, a semiconductor nanowire FET includes a source, a drain and one or more nanowire channels between the source and the drain. A gate electrode, which wraps around the one or more nanowire channels, regulates electron flow through the nanowire channel between the source and drain.
To render semiconductor nanowire devices competitive in terms of device density, stacked semiconductor nanowire devices are typically used. In such devices, two or more semiconductor nanowires are vertically stacked one atop another. One challenge with forming stacked semiconductor nanowire CMOS devices is how to improve the nanowire device performance for p-type FET devices, without adversely affecting the nanowire device performance for the n-type FET devices.